1. Field of the Invention
This invention relates to a high-speed memory device the internal circuitry whereof operates in synchronization with a clock signal, and particularly to a memory device wherewith the current consumed in conjunction with clock signal supply is reduced.
2. Description of the Related Art
With a synchronous DRAM (SDRAM) of the clock-synchronized type, an input buffer inputs externally supplied signals in synchronous with supplied clock signals, the internal circuitry operates in pipeline fashion synchronously with the clock signals, and read out data are output from a data output circuit synchronously with the clock signals. By effecting synchronization with the clock signals, high-speed operation is realized.
Such a SDRAM, from the combination of control signals supplied synchronously with the clock signal, is controlled in an active status, a read status, a write status, and a recharge status, etc. In general, after an active command is received for controlling in the active status, either a read command that effects the read status or a write command that effects the write status is supplied. Last of all, a standby status is effected after receiving a precharge command. At all times when the power-down state is not in effect, the clock signals supplied from the outside are taken in, internal clock signals are generated, and those internal clock signals are supplied to the internal circuitry. In the power-down state, taking in the clock signals is disabled, and no internal clock signals are generated.
The internal circuitry to which the internal clock signals are supplied includes, firstly, an input buffer for inputting data and address signals and the like synchronized with the clock signals, secondly, an internal reading circuit having a clock-synchronized pipeline configuration for reading out data from memory cells, and, thirdly, a data output circuit for outputting the read out data to the outside synchronously with the clock signals. Accordingly, in a conventional clock-synchronized memory device such as a SDRAM, in the non-power-down state, the clock signals taken in are branched and supplied, respectively, to the input buffer, internal read circuit, and data output circuit noted above.
There is a demand, however, for clock-synchronized memory devices to be faster while at the same time consuming less power. Making the clock frequency higher in order to achieve higher speeds involves raising the frequency of drive actions in conjunction with supplying clock signals to the internal circuitry, and, hence, an increase in power consumption. Thus faster speeds and lower power consumption are mutually inconsistent demands.
In particular, the data output circuits, which is one of the components mentioned above to which clock signals are supplied, are positioned adjacent to the data I/O terminals (DQ terminals) that are deployed in a plurality on the chip. Accordingly, the clock signal supply lines for supplying the internal clock signals are lines that extend over long distances from the clock signal supply circuit to the plurality of data output circuits. Such multiple clock signal supply lines that extend over long distances constitute a large load, and the clock signal supply circuit that drives this load requires large drive transistors, which leads, as a result, to large current consumption.
That being so, an object of the present invention is to provide a clock-synchronized memory device wherewith the current consumption is reduced in the clock signal supply circuit for supplying clock signals to the internal circuitry.
Another object of the present invention is to provide a clock-synchronized memory device wherewith the current consumption associated with the supply of clock signals to the data output circuit in the clock signal supply circuit is made small.
In order to realize the object stated above, one aspect of the present invention is that, when the memory is in the non-power-down state, the supply of clock signals to the data output circuit is limited to the read status after the reception of a read command, and no clock signal supply is performed when either the active status or the write status is in effect. In the best aspect, furthermore, in the read status after the reception of a read command, the supply of clock signals to the data output circuit starts after a number of clock signals corresponding to a set CAS latency following the read command, and stops after a number of clock signals corresponding to a set burst length, after the output of the read out data from the data output circuit starts. Accordingly, even in the non-power-down state, clock signals are only supplied during the time required for the read out data to be actually output from the data output circuit to the outside, whereby it is possible to reduce the number of clock signal supply actions that require large current drive.
Furthermore, in another aspect of the present invention, the supply of clock signals to the input buffer that inputs supplied data and address signals synchronized with the clock, in the non-power-down state, is performed both when in the read status and at times other than when in the read status. Furthermore, clock signals are also supplied to the internal read circuit that reads out data contained in the memory cell region noted earlier synchronously with the clock, both when in the read status and at times other than when in the read status. When the memory is in the non-power-down state, the timing for the input signals going to the input buffer cannot be predicted beforehand, wherefore the supply of clock signals to the input buffer is continued irrespective of the read status being in effect. When the memory is in the non-power-down state, moreover, the internal read circuit is performing a pipeline operation, wherefore stopping the clock leads to confusion in the pipeline operation. The supply of clock signals to the internal read circuit, therefore, is continued irrespective of the read status being in effect.
In order to realize the objects stated earlier, one aspect of the present invention is a memory device operating in synchronization with a clock signal, comprising: a memory cell region for storing data; an internal read circuit for reading out data stored in said memory cell region in synchronization with said clock signal; a data output circuit for outputting data read out from said internal read circuit in synchronization with said clock signal; and a clock signal supply circuit for supplying said clock signal to said data output circuit, wherein: said clock signal supply circuit supplies said clock signal to said data output circuit when in a read mode wherein said read data are output from said data output circuit, and does not supply said clock signal to said data output circuit when not in said read mode.
In a preferable embodiment of the present invention, furthermore, the clock signal supply circuit supplies the clock signal to the data output circuit, in the read mode after the reception of a read command, during the time interval from the completion of a number of clock pulses corresponding to a set CAS latency after the reception of the read command, to the completion of a number of clock pulses corresponding to a set burst length after the output of read data from the data output circuit has started.